Description
The Alveo FPGA Cluster enables access to custom hardware acceleration. Read to the official press release here.
Infrastructure
All servers have XRT 2.5.309 installed.
The build server, alveo0.ethz.ch, provides the following tools and development shells:
The alveo1.ethz.ch U250 server is dedicated for QDMA shell deployment. For more information about it, click here
Server |
OS |
Alveo Boards |
Xilinx Shell |
VM |
alveo1.ethz.ch |
Ubuntu 18.04.3 |
U250
U250 |
QDMA 201920.1
QDMA 201920.1 |
alveo1a.ethz.ch
alveo1b.ethz.ch |
alveo2.ethz.ch |
Ubuntu 18.04.3 |
U250
U250 |
XDMA 201830.2
XDMA 201830.2 |
alveo2a.ethz.ch
alveo2b.ethz.ch |
alveo3.ethz.ch |
Ubuntu 18.04.3 |
U250
U280
U280 |
XDMA 201830.2
XDMA 201920.3
XDMA 201920.3 |
alveo3a.ethz.ch
alveo3b.ethz.ch
alveo3c.ethz.ch |
alveo4.ethz.ch |
Ubuntu 18.04.3 |
U250
U280
U280 |
XDMA 201830.2
XDMA 201920.3
XDMA 201920.3 |
alveo4a.ethz.ch
alveo4b.ethz.ch
alveo4c.ethz.ch |
Server |
CPU |
Frequency |
# of Cores |
RAM |
alveo0.ethz.ch |
2x Intel® Xeon® Gold 6248 |
2.50 GHz |
40 |
376 GiB |
alveo1.ethz.ch |
2x Intel® Xeon® Gold 6234 |
3.30 GHz |
16 |
376 GiB |
alveo2.ethz.ch |
2x Intel® Xeon® Gold 6234 |
3.30 GHz |
16 |
376 GiB |
alveo3.ethz.ch |
4x Intel® Xeon® Gold 6234 |
3.30 GHz |
32 |
376 GiB |
alveo4.ethz.ch |
4x Intel® Xeon® Gold 6234 |
3.30 GHz |
32 |
376 GiB |
Booking system
For scheduling accesses to the machines, use the booking system: alveo-booking.ethz.ch
Access to the Cluster
The Alveo Cluster is not accessible directly from the Internet. To access the cluster from outside the ETHZ network, VPN or SSH tunnel must be used. Instructions on how to access the cluster will be sent when Guest Account is created.
Currently, access is through a VM that grants access to a single FPGA. It is possible to reserve VMs that provide access to an entire node with several FPGAs. There is also a VM running InAccel in either single FPGA or multiple FPGA mode (within a single node). We will be adding more options as demand arises.
Registration
To access the cluster, researchers outside ETH should request access through Xilinx University Program. For researchers at ETH, please contact Prof. Gustavo Alonso.
Acknowledgement
We would like to thank Xilinx® for the board donation.