Avalanche - Past Project

Avalanche: Data Processing on Bare Metal

Project Description

The limitations of today's computing architectures are well known: high power consumption, heat dissipation, network and I/O bottlenecks, and the memory wall. Field-programmable gate arrays (FPGAs), user-configurable hardware chips, are promising candidates to overcome these limitations. With tailor-made and software-configured hardware circuits it is possible to process data at very high throughput rates and with extremely low latency. Yet, FPGAs consume orders of magnitude less power than conventional systems. Thanks to their high configurability, they can be used as co-processors in heterogeneous multi-core architectures, and/or directly be placed in critical data paths to reduce the load that hits the system CPU.

In Avalanche we work on a realization of these promises. To this end, we are building a processing stack for FPGA-based database processing. Our Glacier compiler translates a useful subset of a stream query language into hardware circuits, e.g., to make the latency and throughput advantages of FPGAs accessible to financial trading applications. Our recent hardware solution to the frequent item problem significantly outperforms known software solutions—at a fraction of the resource consumption.

Project members
  • Gustavo Alonso (professor)
  • Cagri Balkesen (PhD student)
  • Pratanu Roy (PhD student)
  • Jens Teubner (postdoc)
  • Louis Woods (PhD student)

Former members:



Avalanche was supported by the Swiss National Science Foundation.